The present invention relates in general to the semiconductor technology and more particularly to structures and methods for testing wafer.
The rapid advancement in the semiconductor industry has enabled manufacturing of highly complex integrated circuits (ICs). Such ICs are being fabricated on large wafers capable of housing a greater number of dies. Also, with the advancement in the IC packaging technology, smaller packages with significantly higher pin-count have become commercially available. A larger number of pads can thus be placed on each die. This has in turn resulted in a significantly more complex set of test requirements and a substantial increase in the time required to test all dies on a wafer.
FIG. 1 shows a top view of a wafer 100 having multiple dies 102 organized in rows and columns separated by horizontal scribe lines 104 and vertical scribe lines 106. After wafer sort (i.e., testing all the dies on a wafer to identify non-functional dies), the good dies are extracted from the wafer by sawing along the vertical and horizontal scribe lines and then placed in the desired packages. Wafer sort is usually carried out using a probe card connected to a tester. The probe card sequentially contacts each die on the wafer until all dies have been tested.
Techniques wherein multiple dies are tested simultaneously are widely used to reduce wafer sort time. However, the number of dies that can be tested at the same time is limited by the number of pins that a tester can support divided by the number of pins on each die (the current testers are limited to few hundred pins).
Accordingly, there is a need for structures and methods for efficiently testing dies on a wafer.